1. Field of the Invention
The present invention relates to floating point arithmetic units and, more particularly, to addition and subtraction operations performed upon floating point numbers in a floating point unit of a microprocessor.
2. Description of the Related Art
Microprocessors typically include floating point units to accommodate floating point arithmetic operations. A floating point number consists of two parts: a fraction f and an exponent e. The two parts represent a number that is obtained by multiplying the fraction f times a radix that is raised to the power of e. The fraction f of the floating point number is often referred to as the mantissa.
A 32-bit binary format for a floating point number is shown in FIG. 1. The exemplary floating point number of FIG. 1 includes a 24-bit fractional part, a 7-bit signed (positive or negative) exponent, and a sign bit that indicates the sign of the number.
Addition and subtraction operations associated with floating point numbers are somewhat more complicated than addition and subtraction of integer numbers. Before actually performing an addition or subtraction operation upon the mantissas of the numbers, since the numbers are typically normalized, the relative magnitudes of the exponents must be compared to align the mantissas, if necessary. If the two exponents are equal, thus indicating that the mantissas are already aligned, the arithmetic operation can be effectuated by directly adding (or subtracting) the mantissas according to the desired operation. However, if the exponents are not equal, then the mantissa with the smaller exponent is typically shifted to the right by a number of positions equal to the difference between the exponents. Once the mantissas have been aligned, an arithmetic operation of addition or subtraction may be performed upon the aligned mantissas in accordance with the desired operation. Subsequently, post normalization of the result is carried out. It is noted that subtraction may be carried out by two's complementing the subtrahend and performing an addition operation. For the special case in which one of the operands is equal to zero, other specific operations may be performed.
FIG. 2 illustrates a generalized block diagram of aspects of an exemplary floating point arithmetic unit. As illustrated in FIG. 2, the two floating point numbers A1 and B1 to be added (or subtracted) are compared within a comparator 20 to determine their relative magnitudes. The exponent value of the floating point number with the smaller exponent is subtracted from the exponent value of the floating point number with the larger exponent by subtractor 22. After subtracting the value of the smaller exponent from the value of the larger exponent, the result is provided to a shift unit 24 which shifts the mantissa associated with the floating point number having the smaller exponent by a number of positions to the right which is equal to the difference in the exponent values. Subsequently, the shifted mantissa along with the unshifted mantissa of the floating point number having the larger exponent are operated upon (either added or subtracted) by an adder/subtractor unit 26 depending upon the desired operation (i.e. add or subtract) as well as upon the signs of the floating point numbers. The result conveyed from the adder/subtractor unit 26 may then be normalized by normalization unit 28.
The operation of the circuit of FIG. 2 may be illustrated by the following example. Consider a situation in which two normalized operands are to be added as follows: ##EQU1## The circuit first subtracts the smaller exponent value of 4 (in decimal) from the larger exponent value of 6, which results in a value of 2. The floating point number having the smaller exponent is accordingly right shifted by two positions and operated upon as follows: ##EQU2## As shown above, the exponent of the right shifted value is further increased by 2. The fractional portions or mantissas of the floating point numbers are then added to obtain the result. At this point, the result may or may not require normalization, which is effectuated by normalization unit 28 if appropriate.
Not surprisingly, it is important in high performance microprocessors to effectuate floating point operations quickly. From the foregoing description, however, it is evident that substantial time may be required to finish the subtraction of the exponents to determine the amount by which a particular mantissa must be shifted. It would be desirable to perform this shift operation more expeditiously.